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PI6C410
Clock Generator for Intel PCI-Express Desktop Chipset
Product Features
* 14.318 MHz Crystal Input * Selectable of 100, 133, 166, 200, 266, 333, and 400MHz CPU Output Frequencies * SMBus: Power Management Control * Spread Spectrum support (-0.5% down spread) * Packaging (Pb-free & Green available): -56-Pin SSOP (V) -56-Pin TSSOP (A)
Product Description
PI6C410 is a high-speed, low-noise clock generator designed to work with Intel Desktop PCI-Express Chipset. Spread Spectrum PLL based clock generator reduce EMI emission and support a wide range of frequencies. Jitter Performance * < 85ps Cycle to Cycle CPU clock jitter * < 350ps Cycle to Cycle 48MHz clock jitter * < 500ps Cycle to Cycle PCI clock jitter * < 125ps Cycle to Cycle SRC clock jitter * < 1000ps Cycle to Cycle REF clock jitter Skew Performance * < 100ps Output to output CPU clock skew * < 500ps Output to output PCI clock skew * < 250ps Output to output SRC clock skew
Output Features
* Two Pairs of Differential CPU Clocks * One selectable of CPU/SRC Clock * Six Pairs of SRC Clocks * Nine PCI Clocks * One 48 MHz USB clock * One REF clock * One 96 MHz Differential clock
Logic Block Diagram
XTAL_IN XTAL_OUT XTAL OSC PLL 2 /2 PLL 1 SDA SCL Div
DOT_96 DOT 96# USB_48 REF PCI [0:5] PCIF[0:2]
Pin Description
VDD_PCI VSS_PCI PCI_3 PCI_4 PCI_5 VSS_PCI VDD_PCI PCIF_0 / ITP_EN PCIF_1 PCIF_2 VDD_48 USB_48 VSS_48 DOT_96 DOT_96# FS_B / TEST_MODE VTT_PWRGD# / PWRDWN FS_A SRC_1 SRC_1# VDD_SRC SRC_2 SRC_2# SRC_3 SRC_3# SRC_4 SRC_4# VDD_SRC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PCI_2 PCI_1 PCI_0 FS_C / TEST_SEL REF VSS_REF XTAL_IN XTAL_OUT VDD_REF SDA SCL VSS_CPU CPU_0 CPU_0# VDD_CPU CPU_1 CPU_1# IREF VSS_A VDD_A CPU2_ITP / SRC7 CPU2_ITP# / SRC7# VDD_SRC SRC_6 SRC_6# SRC_5 SRC_5# VSS_SRC
SMBus Logic
Div FS_A FS_B / TEST_MODE FS_C / TEST_SEL VTT_PWRGD# / PWRDWN PCIF_0 / ITP_EN C O N T R O L
SRC [1:6] SRC [1:6]# CPU2_ITP / SRC7 CPU2_ITP# / SRC7#
Div
CPU[0:1] CPU[0:1]#
1
PS8734A
09/02/04
PI6C410 Clock Generator for Intel PCI-Express Desktop Chipset Pin Description
Pin Name REF XTAL_IN XTAL_OUT CPU[0:1] & CPU[0:1]# SRC[1:6] & SRC[1:6]# CPU2_ITP / SRC_7 & CPU2_ITP# / SRC_7# PCIF_0 / ITP_EN PCIF[1:2] PCI[0:5] USB_48 DOT_96 & DOT_96# FS_A FS_B / TEST_MODE FS_C / TEST_SEL IREF VTT_PWRGD# / PWRDWN SDA SCL VDD_PCI VDD_48 VDD_SRC VDD_CPU VDD_REF VSS_PCI VSS_48 VSS_SRC VSS_CPU VSS_REF VDD_A VSS_A Type Output Input Output Output Output Pin No 52 50 49 40, 41, 43, 44 19, 20, 22, 23, 24, 25, 26, 27, 30, 31, 32, 33 35, 36 8 9, 10 3, 4, 5, 54, 55, 56 12 14, 15 18 16 53 39 17 47 46 1, 7 11 21, 28, 34 42 48 2, 6 13 29 45 51 37 38 Descriptions 3.3V 14.31818MHz output 14.31818MHz crystal input 14.31818MHz crystal output Differential CPU outputs Differential Serial Reference Clock outputs Selectable Differential CPU or SRC clock output ITP_EN = 0 @ Vtt_Pwrgd# assertion = SRC ITP_EN = 1 @ Vtt_Pwrgd# assertion = CPU 33MHz clock output / CPU2 select when HIGH 33MHz clocks outputs (free running) 33MHz clocks outputs 48MHz clock output 96MHz differential clock output 3.3V LVTTL inputs for CPU frequency selection 3.3V LVTTL inputs for CPU frequency selection / Test Mode select: 0 = HiZ, 1 = Ref/N 3.3V LVTTL inputs for CPU frequency selection / Test Mode select if pulled to 3.3V when Vtt_Pwrgd# is asserted LOW External resistor connection for internal current reference 3.3V LVTTL Level sensitive strobe used to determine to latch the FS_A, FS_B/TEST_MODE, FS_C/TEST_SEL and PCIF0/ ITP_EN inputs (active low) / 3.3V LVTTL active high input for Power Down operation. SMBus compatible SDATA SMBus compatible SCLOCK 3.3V Power Supply for Outputs 3.3V Power Supply for Outputs 3.3V Power Supply for Outputs 3.3V Power Supply for Outputs 3.3V Power Supply for Outputs Ground for Outputs Ground for Outputs Ground for Outputs Ground for Outputs Ground for Outputs 3.3V Power Supply for PLL Ground for PLL
Output Input / Output Output Output Output Output Input Input Input Input Input I/O Input Power Power Power Power Power Ground Ground Ground Ground Ground Power Ground
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PS8734A
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PI6C410 Clock Generator for Intel PCI-Express Desktop Chipset Functionality
Frequency Selection
FS_C 1 0 0 0 0 1 1 1 FS_B 0 0 1 1 0 0 1 1 FS_A 1 1 1 0 0 0 0 1 CPU 100MHz 133MHz 166MHz 200MHz 266MHz 333MHz 400MHz Reserved SRC 100MHz 100MHz 100MHz 100MHz 100MHz 100MHz 100MHz 100MHz PCIF / PCI 33MHz 33MHz 33MHz 33MHz 33MHz 33MHz 33MHz 33MHz REF 14.318MHz 14.318MHz 14.318MHz 14.318MHz 14.318MHz 14.318MHz 14.318MHz 14.318MHz DOT_96 96MHz 96MHz 96MHz 96MHz 96MHz 96MHz 96MHz 96MHz USB_48 48MHz 48MHz 48MHz 48MHz 48MHz 48MHz 48MHz 48MHz Note 1 1 1 1 1 1 1 1
Notes: 1. Refer to DC Electrical Characteristics for FS_A, FS_B and FS_C (Vih_FS, Vil_FS) threshold levels
Test Mode Selection
TEST_MODE 1 0 CPU REF/N Hi-Z SRC REF/N Hi-Z PCIF / PCI REF/N Hi-Z REF REF Hi-Z DOT_96 REF/N Hi-Z USB_48 REF/N Hi-Z Note 2 2
Notes: 2. Test mode will occur where the SMBus Bit 6 of Byte 6 = 1, or FS_C/TEST_SEL is set to logic high level.
PWRDWN Functionality
PWRDWN 0 1 CPU Normal Iref x 2 or Float CPU# Normal Float SRC Normal Iref x 2 or Float SRC# Normal Float PCIF / PCI 33MHz Low REF 14.318MHz Low DOT_96 Normal Iref x 2 or Float DOT_96# Normal Float USB_48 48MHz Low
3
PS8734A
09/02/04
PI6C410 Clock Generator for Intel PCI-Express Desktop Chipset Serial Data Interface (SMBus)
PI6C410 is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit address and read/write bit as shown below.
Address Assignment
A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W 1/0
Data Protocol
1 bit Start bit 7 bits Slave Addr 1 R/W 1 Ack 8 bits Register offset 1 Ack 8 bits Byte Count =N 1 Ack 8 bits Data Byte 0 1 Ack ... 8 bits Data Byte N -1 1 Ack 1 bit Stop bit
Notes: 1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
Data Byte 0: Control Register
Bit 0 1 2 3 4 5 6 7 Reserved SRC_1 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) SRC_2 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) SRC_3 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) SRC_4 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) SRC_5 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) SRC_6 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) CPU_2 / SRC_7 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) Descriptions Type RW RW RW RW RW RW RW RW 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled SRC_1 SRC_2 SRC_3 SRC_4 SRC_5 SRC_6 CPU_2 / SRC_7 19, 20 22, 23 24, 25 26, 27 30, 31 32, 33 35, 36 NA NA NA NA NA NA NA Power Up Condition Output(s) Affected Pin Source Pin
4
PS8734A
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PI6C410 Clock Generator for Intel PCI-Express Desktop Chipset Data Byte 1: Control Register
Bit Descriptions Type Power Up Condition Output(s) Affected Pin 3, 4, 5, 8, 9, 10, 19, 20, 22, 23, 24, 25, 26, 27, 30, 31, 32, 33, 35, 36, 40, 41, 43, 44, 54, 55, 56 43, 44 40, 41 Source Pin
0
Spread Spectrum 1 = On, 0 = Off
RW
0 = Spread off
CPU[0:2], SRC[1:7], PCI[0:5], PCIF[0:2]
NA
1 2 3 4 5 6 7
CPU_0 output enable 1 = Enabled, 0 = Disabled (Hi-Z) CPU_1 output enable 1 = Enabled, 0 = Disabled (Hi-Z) Reserved REF Output Enable 1 = Enabled, 0 = Disabled USB_48 Output Enable 1 = Enabled, 0 = Disabled DOT_96 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) PCIF_0 Output Enable 1 = Enabled, 0 = Disabled
RW RW RW RW RW RW RW
1 = Enabled 1 = Enabled
CPU_0, CPU_0# CPU_1, CPU_1#
NA NA
1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled
REF USB_48 DOT_96 & DOT96# PCIF_0
52 12 14, 15 8
NA NA NA NA
Data Byte 2: Control Register
Bit 0 1 2 3 4 5 6 7 Descriptions PCIF_1 Output Enable 1 = Enabled, 0 = Disabled PCIF_2 Output Enable 1 = Enabled, 0 = Disabled PCI_0 Output Enable 1 = Enabled, 0 = Disabled PCI_1 Output Enable 1 = Enabled, 0 = Disabled PCI _2 Output Enable 1 = Enabled, 0 = Disabled PCI _3 Output Enable 1 = Enabled, 0 = Disabled PCI _4 Output Enable 1 = Enabled, 0 = Disabled PCI _5 Output Enable 1 = Enabled, 0 = Disabled Type RW RW RW RW RW RW RW RW Power Up Condition 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled Output(s) Affected PCIF_1 PCIF_2 PCI_0 PCI_1 PCI_2 PCI_3 PCI_4 PCI_5 Pin 9 10 54 55 56 3 4 5 Source Pin NA NA NA NA NA NA NA NA
5
PS8734A
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PI6C410 Clock Generator for Intel PCI-Express Desktop Chipset Data Byte 3: Control Register
Bit 0 1 2 3 4 5 6 7 Descriptions Reserved SRC_1 Output Control 0 = Free Running SRC_2 Output Control 0 = Free Running SRC_3 Output Control 0 = Free Running SRC_4 Output Control 0 = Free Running SRC_5 Output Control 0 = Free Running SRC_6 Output Control 0 = Free Running SRC_7 Output Control 0 = Free Running Type RW RW RW RW RW RW RW RW 0 = Free running 0 = Free running 0 = Free running 0 = Free running 0 = Free running 0 = Free running 0 = Free running SRC_1 SRC_2 SRC_3 SRC_4 SRC_5 SRC_6 SRC_7 19, 20 22, 23 24, 25 26, 27 30, 31 32, 33 35, 36 NA NA NA NA NA NA NA Power Up Condition Output(s) Affected Pin Source Pin
Data Byte 4: Control Register
Bit 0 1 2 3 4 5 6 7 Descriptions CPU_0 Output Control 0 = Free Running CPU_1 Output Control 0 = Free Running CPU_2 Output Control 0 = Free Running PCIF_0 Output Control 0 = Free Running PCIF_1 Output Control 0 = Free Running PCIF_2 Output Control 0 = Free Running DOT_Pwrdwn drive mode 1 = Hi-Z, 0 = Driven in Pwrdwn Reserved Type RW RW RW RW RW RW RW RW Power Up Condition 0 = Free running 0 = Free running 0 = Free running 0 = Free running 0 = Free running 0 = Free running 0 = Driven in power down Output(s) Affected CPU_0 CPU_1 CPU_2 PCIF_0 PCIF_1 PCIF_2 DOT_96 & DOT_96# Pin 43, 44 40, 41 35, 36 8 9 10 14, 15 Source Pin NA NA NA NA NA NA NA
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PS8734A
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PI6C410 Clock Generator for Intel PCI-Express Desktop Chipset Data Byte 5: Control Register
Bit 0 1 2 Descriptions CPU_0 Pwrdwn drive mode 1 = Hi-Z, 0 = Driven in Pwrdwn CPU_1 Pwrdwn drive mode 1 = Hi-Z, 0 = Driven in Pwrdwn CPU_2 Pwrdwn drive mode 1 = Hi-Z, 0 = Driven in Pwrdwn SRC_Pwrdwn drive mode 1 = Hi-Z, 0 = Driven in Pwrdwn CPU_0 CPU_Stop drive mode 1 = Hi-Z, 0 = Driven in CPU_Stop CPU_1 CPU_Stop drive mode 1 = Hi-Z, 0 = Driven in CPU_Stop CPU_2 CPU_Stop drive mode 1 = Hi-Z, 0 = Driven in CPU_Stop SRC_Stop drive mode 1 = Hi-Z, 0 = Driven in PCI_Stop Type RW RW RW Power Up Condition 0 = Driven in power down 0 = Driven in power down 0 = Driven in power down 0 = Driven in power down 0 = Driven in CPU_Stop 0 = Driven in CPU_Stop 0 = Driven in CPU_Stop 0 = Driven in PCI_Stop Output(s) Affected CPU_0 & CPU_0# CPU_1 & CPU_1# CPU_2 & CPU_2# SRC[1:7] & SRC[1:7]# Pin 43, 44 40, 41 35, 36 19, 20, 22, 23, 24, 25, 26, 27, 30, 31, 32, 33, 35, 36 43, 44 Source Pin NA NA NA
3
RW
NA
4
RW
CPU_0 & CPU_0#
NA
5
RW
CPU_1 & CPU_1#
40, 41
NA
6
RW
CPU_2 & CPU_2#
35, 36 19, 20, 22, 23, 24, 25, 26, 27, 30, 31, 32, 33, 35, 36
NA
7
RW
SRC[1:7] & SRC[1:7]#
NA
7
PS8734A
09/02/04
PI6C410 Clock Generator for Intel PCI-Express Desktop Chipset Data Byte 6: Control Register
Bit Descriptions FS_A Reflects the value of the FS_A pin sampled on power up 0 = FS_A was low during Vtt_Pwrgd# assertion FS_B Reflects the value of the FS_B pin sampled on power up 0 = FS_B was low during Vtt_Pwrgd# assertion FS_C Reflects the value of the FS_C pin sampled on power up 0 = FS_C was low during Vtt_Pwrgd# assertion PCI_Stop Output Control 0 = Enabled, all stoppable PCI and SRC clocks are stopped 1 = Disabled REF Output Drive Strength 0 = 1x, 1 =2x Reserved Test Clock Mode Entry Control 0 = Disabled, 1 = REF/N or Hi-Z Type Power Up Condition Externally Selected Output(s) Affected Pin 35, 36, 40, 41, 43, 44 Source Pin
0
R
CPU[0:2]
NA
1
R
Externally Selected
CPU[0:2]
35, 36, 40, 41, 43, 44
NA
2
R
Externally Selected
CPU[0:2]
35, 36, 40, 41, 43, 44 3, 4, 5, 8, 9, 10, 19, 20, 22, 23, 24, 25, 26, 27, 30, 31, 32, 33, 35, 36 52
NA
3
RW
1 = Disabled
All PCI & SRC clocks except PCIF and SRC clocks set to free-running REF
NA
4 5 6
RW RW RW
1 = 2X
NA
0 = Disabled 3, 4, 5, 8, 9, 10, 12, 14, 15, 19, 20, 22, 23, 24, 25, 26, 27, 30, 31, 32, 33, 35, 36, 40, 41, 43, 44, 52, 54, 55, 56
7
Test Clock Mode 0 = Hi-Z, 1 = REF/N
RW
0 = Hi-Z
CPU[0:2], SRC[1:7], PCI[0:5], PCIF[0:2], REF, USB_48, DOT_96
NA
Data Byte 7: Pericom ID Register
Bit 0 1 2 3 4 5 6 7 Revision Code Vendor ID Descriptions Type R R R R R R R R Power Up Condition 0 0 0 0 1 0 1 0 Output(s) Affected NA NA NA NA NA NA NA NA Pin NA NA NA NA NA NA NA NA
8
PS8734A
09/02/04
PI6C410 Clock Generator for Intel PCI-Express Desktop Chipset Power Down (PWRDWN assertion)
PWRDWN CPU, 133 MHz CPU#, 133 MHz SRC, 100 MHz SRC#, 100 MHz USB, 48 MHz DOT, 96 MHz DOT#, 96 MHz PCI REF
Figure 1, Power down sequence
Power Down (PWRDWN de-assertion)
PWRDWN CPU, 133 MHz CPU#, 133 MHz SRC, 100 MHz SRC#, 100 MHz USB, 48 MHz DOT, 96 MHz DOT#, 96 MHz PCI REF Tdrive_PwrDwr < 300us, > 200mV Tstable < 1.8ms
Figure 2, Power down de-assert sequence
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PS8734A 09/02/04
PI6C410 Clock Generator for Intel PCI-Express Desktop Chipset Tristate Specifications
Signal CPU[0:2], SRC[1:7], DOT96 Pwrdwn pin 0 1 1 Pwrdwn Tristate Bit X 0 1 Stoppable Outputs Running Driven @ Iref x 2 Tristate Non-stop Outputs Running Driven @ Iref x 2 Tristate
Spread Spectrum Specifications
PI6C410 supports Spread Spectrum clocking and can be enabled and disabled via SMBus control. The maximum Spread Spectrum Modulation is -0.5% down spread with frequency from 30KHz to 33KHz. SSC ON CPU @ 399.000MHz CPU @ 332.500MHz CPU @ 266.000MHz CPU @ 199.500MHz CPU @ 166.250MHz CPU @ 133.000MHz CPU @ 99.750MHz SRC @ 99.750MHz PCIF / PCI @ 33.250MHz Tperiod Min 2.4993 2.9991 3.7489 4.9985 5.9982 7.4978 9.997 9.997 29.991 Max 2.5133 3.016 3.77 5.0266 6.032 7.54 10.0533 10.0533 30.1598 SSC OFF CPU @ 400.000MHz CPU @ 333.333MHz CPU @ 266.666MHz CPU @ 200.000MHz CPU @ 166.666MHz CPU @ 133.333MHz CPU @ 100.000MHz SRC @ 100.000MHz PCIF / PCI @ 33.333MHz Tperiod Min 2.4993 2.9991 3.7489 4.9985 5.9982 7.4978 9.997 9.997 29.991 Max 2.5008 3.0009 3.7511 5.0015 6.0018 7.5023 10.003 10.003 30.009 ns Unit
Crystal Recommendations
Frequency 14.31818MHz Cut AT Loading Parallel Load Cap 20pF Drive Max. 0.1mW Shunt Cap Max. 5pF Motional Cap Max. 0.016pF Tolerance Max. 35ppm Stability Max. 30ppm Aging Max. 5ppm
Notes: 1. External trim capacitors (Ce) are required by using this formula Ce = 2*CL - (Cs + Ci). Typical Ce = 33pF when Crystal Load = 20pF, Trace capacitance (Cs) = 2.8pF and XTAL pins capacitance = 4.5pF.
10
PS8734A
09/02/04
PI6C410 Clock Generator for Intel PCI-Express Desktop Chipset Current-mode output buffer characteristics of CPU, SRC, and DOT
Vdd (3.3V 5%)
Slope ~1/Ro Ro lout
Ros lout 0V 0.85V
Vout = 0.85V Max.
Figure 3. Simplified diagram of a current-mode output buffer
Host Clock Buffer Characteristics
Minimum RO ROS VOUT 3000 unspecified N/A Maximum N/A unspecified 850mV
Current Accuracy
Conditions IOUT VDD = 3.30 5% Configuration Rref = 475 1% Iref = 2.32mA Load Nominal test load for given configuration Min. -12% INOMINAL Max. +12% INOMINAL
Hot Clock Output Current
Board Target Trace/Term Z 100 (100 differential 8% coupling ratio) Reference R, IREF = VDD/(3xRr) RREF = 475 1%, IREF = 2.32mA Output Current IOH = 6 x Iref VOH @ Z 0.7V @ 50
11
PS8734A
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PI6C410 Clock Generator for Intel PCI-Express Desktop Chipset Absolute Maximum Ratings (Over operating free-air temperature range)
Symbol VDD_A VDD VIH VIL Ts VESD Parameters 3.3V Core Supply Voltage 3.3V I/O Supply Voltage Input High Voltage Input Low Voltage Storage Temperature ESD Protection -0.5 -65 2000 150 C V Min. -0.5 -0.5 Max. 4.6 4.6 4.6 V Units
Notes: 1. Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
Configuration test load board termination
Rs 33-Ohms 5% PI6C410
Clock TLA Clock# TLB
Rs 33-Ohms 5% Rp 49.9-Ohms 1% 2pF 5%
475-Ohms 1%
Rp 49.9-Ohms 1%
2pF 5%
Notes: 1. Maximum 10" trace length for CPU @ 200 MHz, 16" trace for SRC @ 100 MHz.
Figure 4. Configuration test load board termination
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PS8734A
09/02/04
PI6C410 Clock Generator for Intel PCI-Express Desktop Chipset DC Electrical Characteristics (VDD = 3.35%, VDD_A = 3.35%)
Symbol VDD_A VDD VIH VIL IIK VIH_FS VIL_FS VOH VOL Parameters 3.3V Core Supply Voltage 3.3V I/O Supply Voltage 3.3V Input High Voltage 3.3V Input Low Voltage Input Leakage Current 3.3V Input High Voltage 3.3V Input Low Voltage 3.3V Output High Voltage 3.3V Output Low Voltage IOH = -1mA IOL = 1mA CPU, SRC, DOT: IOH = 6 x Iref, Iref = 2.32mA IOH Output High Current USB REF, PCI USB IOL Output Low Current REF, PCI Cin Cxtal Cout Lpin IDD ISS ISS Ta Input Pin Capacitance Xtal Pin Capacitance Output Pin Capacitance Pin Inductance Power Supply Current Power Down Current Power Down Current Ambient Temperature VDD = 3.465V, FCPU = 400MHz Driven outputs Tristate outputs 0 VOH = 1.0V VOH = 3.135V VOH = 1.0V VOH = 3.135V VOL = 1.95V VOL = 0.4V VOL = 1.95V VOL = 0.4V 3 3 30 38 5 5 6 7 500 70 12 70 C mA nH pF 29 27 -33 -33 12.2 15.6 -29 -23 mA 0 < VIN < VDD VDD Condition Min. 3.135 3.135 2.0 VSS - 0.3 -5 0.7 VSS - 0.3 2.4 0.4 Max. 3.465 3.465 VDD + 0.3 0.8 +5 VDD + 0.3 0.35 V A V Units
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PS8734A
09/02/04
PI6C410 Clock Generator for Intel PCI-Express Desktop Chipset AC Electrical Characteristics (VDD = 3.35%, VDD_A = 3.35%)
Symbol Trise / Tfall Trise / Tfall Trise / Tfall Trise / Tfall Tskew Tskew Tskew Tjitter Tjitter Tjitter Tjitter Tjitter Tjitter VHIGH VLOW Vcross Vcross TDC TDC Tstable Tdrive Pwrdwn Trise / Tfall Pwrdwn Outputs CPU, SRC, DOT PCI/PCIF, REF USB CPU, SRC, DOT CPU, SRC, DOT CPU SRC PCI/PCIF, REF CPU SRC DOT PCI/PCIF USB REF CPU, SRC, DOT CPU, SRC, DOT CPU, SRC, DOT CPU, SRC, DOT CPU, SRC, DOT Parameters Rise and Fall Time (measured between 0.175V to 0.525V) Rise and Fall Time (measured between 0.4V to 2.4V) Rise and Fall Time (measured between 0.4V to 2.4V) Rise and Fall Time Variation Rise/Fall Matching CPU - CPU Skew SRC - SRC Skew PCI - PCI Skew / REF - REF Skew (measured at 1.5V) Cycle - Cycle Jitter Cycle - Cycle Jitter Cycle - Cycle Jitter Cycle - Cycle Jitter (measured at 1.5V) Cycle - Cycle Jitter (measured at 1.5V) Cycle - Cycle Jitter (measured at 1.5V) Voltage High including overshoot Voltage Low including undershoot Absolute crossing poing voltages Total Variation of Vcross over all edges Duty Cycle 45 45 660 -300 250 550 140 55 55 <1.8 300 5.0 % % ms s ns Fig 2 3, 5 6, 7 Min 175 0.5 1.0 Max. 700 2.0 ns 2.0 125 20 100 250 500 85 125 250 500 350 1000 1150 mV 3, 4 6 7 6 ps ps % 7 3, 4 3, 5 6 3, 5 Units ps Notes 3, 4 6
REF, USB, PCI/PCIF Duty Cycle (measured at 1.5V) All clock stabilization from power-up Differential output enable after PwrDwn de-assertion PwrDwn rise and fall time
Notes: 3. Test configuration is Rs = 33.2 Ohms, Rp = 49.9 Ohms, and 2pF. 4. Measurement taken from Single Ended waveform. 5. Measurement taken from Differential waveform. 6. PCI, PCIF, and REF outputs minimum loading = 10pF, Maximum loading = 30pF. 7. USB output minimum loading = 10pF, Maximum loading = 20pF.
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PS8734A
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PI6C410 Clock Generator for Intel PCI-Express Desktop Chipset Packaging Mechcanical: 56-Pin SSOP (V)
56
.291 .299 7.39 7.59
.396 .416 10.06 10.56
Gauge Plane
.010 0.25
1
.02 .04 0.51 1.01
.720 18.29 .730 18.54
.008 0.20 Nom.
.015 0.381 x 45 .025 0.635
.110 2.79 Max
.025 BSC 0.635
.008 .0135 0.20 0.34
X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS
0-8
.008 0.20 .016 0.40
Packaging Mechcanical: 56-Pin TSSOP (A)
56
.236 .244
6.0 6.2
1
.547 .555
13.9 14.1
1.20 .047 Max.
SEATING PLANE
.004 0.09 .008 0.20
.0197 BSC 0.50
X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS
.007 .011
0.17 0.27
.002 .006 0.05 0.15
0.45 .018 0.75 .030
.319 BSC 8.1
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PS8734A
09/02/04
PI6C410 Clock Generator for Intel PCI-Express Desktop Chipset Ordering Information:
Ordering Code PI6C410A PI6C410V PI6C410VE Packaging Code A V V Package Type 56-Pin, 240mil wide, 0.5mm pitch TSSOP 56-Pin, 300mil wide, 0.64mm pitch SSOP Pb-free & Green 56-Pin, 300mil wide, 0.64mm pitch SSOP
Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com
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PS8734A 09/02/04

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